In the packaging of integrated circuits, device dies or packages are packaged onto package substrates, which include metal connections that are used to route electrical signals between opposite sides of the package substrates. The device dies may be bonded onto one side of a package substrate using flip chip bonding, and a reflow is performed to melt the solder balls that interconnect the dies and the package substrate.
The package substrates may use materials that can be easily laminated. In addition, organic materials may be used as the dielectric materials of the package substrate. These materials, however, are prone to warpage caused by elevated temperatures used in the reflow of the solder. Furthermore, during the bonding process, since the device dies and the package substrates have significantly different Coefficients of Thermal Expansion (CTEs), the warpage in the dies and the package substrates is worsened. For example, the silicon in the device dies has a CTE close to about 3.2, while the package substrates may have a CTE between about 17 and 10, or even higher. The warpage in the package substrates may cause irregular joints and/or bump cracks. As a result, the yield of the packaging process is adversely affected.